The race to secure embedded devices against future quantum attacks is moving from theory into silicon, and SEALSQ intends to make that tangible at Electronica 2026, the major electronics trade fair running November 10-13 in Munich. The company will unveil two quantum-resistant chips and a new application-specific integrated circuit design concept, alongside a quantum-computer mock-up meant to help visitors grasp why this transition matters now rather than later.
Why Chipmakers Are Moving Early
Quantum computers capable of breaking widely used public-key cryptography do not yet exist at scale, but the concern among security architects is less about today's threat and more about data harvested now and decrypted later. Devices with long operational lifespans, such as smart meters and industrial gateways, are often deployed for a decade or more, meaning cryptography chosen today must remain resilient well into the 2030s and beyond. That logic underpins the centerpiece of SEALSQ's showcase: the VaultIC409, a secure element currently undergoing Common Criteria EAL5+ certification, built on the company's QS7001 platform.
The chip is designed to function as a hardware Root of Trust, the foundational layer of trust that verifies a device's identity and the integrity of its software before anything else runs. Because post-quantum algorithms such as ML-KEM and ML-DSA require significantly larger keys and certificates than older RSA or elliptic-curve methods, the VaultIC409 includes dedicated acceleration for both classical and post-quantum cryptography, communicating over a standard Serial Peripheral Interface. At the fair, SEALSQ plans a live TLS 1.3 demonstration to show the chip negotiating secure connections in practice. Engineering samples are expected in the second quarter of 2027, with the chip aimed at the same markets as its predecessor, the VaultIC408.
A Trusted Platform Module Built for the Quantum Transition
Alongside the secure element, SEALSQ is presenting QVault TPM, a Trusted Platform Module that implements the Trusted Computing Group's post-quantum command set directly in hardware. It generates and stores ML-DSA and ML-KEM keys alongside conventional RSA and ECC keys, giving manufacturers a way to support secure boot, device identity and attestation while migrating gradually rather than abruptly to quantum-resistant algorithms. Integration with wolfSSL's wolfTPM stack means developers can reach these post-quantum functions through an established, widely used interface instead of proprietary tooling - a detail that matters for adoption, since embedded developers tend to resist locking themselves into closed ecosystems. The product line is pursuing both FIPS 140-3 and TCG certifications, standards that carry weight in regulated industries such as energy and healthcare.
Custom Silicon and a Collaborative Security Message
Through its subsidiary IC'Alps, acquired in August 2025, SEALSQ is also introducing QASIC, a design service for building post-quantum security directly into custom application-specific chips rather than bolting it on afterward. IC'Alps contributes expertise in analog, digital and mixed-signal design along with functional safety work, which matters for sectors like automotive and medical devices where certification requirements are strict and failure tolerances are low.
The company's presence extends beyond its own booth: on November 11, SEALSQ joins NXP and Infineon for a roundtable on "Physical AI at the Edge for Industrial Security," suggesting that post-quantum readiness is increasingly viewed as an industry-wide coordination problem rather than a single-vendor product line. Visitors will also be able to learn about SEALSQ's silicon quantum-computing partner, tying the hardware demonstrations to the broader quantum-computing context driving this entire shift. For manufacturers designing products with multi-year lifecycles, the message from Munich is straightforward: cryptographic choices made now will determine whether tomorrow's connected devices remain trustworthy once quantum computing matures.